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preliminary rev. 0.4 11/07 copyright ? 2007 by silicon laboratories SI3460 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI3460 ieee 802.3af pse i nterface and dc-dc c ontroller features applications description the SI3460 is a single-port ?48 v power management controller for ieee 802.3af-comp liant power sourcing e quipment (pse). designed to minimize system cost and ease of implementation in embedded pse endpoint (switches) or midspan (p ower injector) a pplications, the SI3460 operates directly from a 12 or 15 v input supply and integrates a digital pwm-based dc-dc converter for generating the ?48 v pse output supply. the ieee-required powered device (pd) detection feature uses a robust 3-point algori thm to avoid false detection events. the SI3460's reference design kit also provides full ieee-compliant classification and pd disconnect. intelligent protection circuitry includes input undervoltage lockout (uvlo), current limiting, and output short circuit protection. the SI3460 is designed to operate completely independently of host processor control. an led status signal is provided to indicate th e port status, including detect, power good, and output fault event information for use within the host system. the SI3460 is pin-programmable to support endpoint and midspan applications, as well as ea ch of the different classification power levels specified by the ieee 802.3af standard. a comprehensive referenc e design kit is available (SI3460-evb), including a complete schematic and bom (bill-of-materials) for the dc- dc converter and pse functions. ieee 802.3af? comp liant pse and dc-dc controller autonomous operation requires no host processor interface complete reference design available, including SI3460 controller, pse firmware, and schematic: low-cost bom with compact pcb footprint operates directly from a +12 or +15 v isolated supply dc-dc controller generates ?48 v pse output for selv compatibility with telephony interfaces supports up to 15.4 w maximum output power (class 0) robust 3-point detection algorithm eliminates false detection events ieee-compliant classification ieee-compliant disconnect inrush current control short-circuit output fault protection led status signal (detect, power good, output fault) unh interoperability test lab test report available extended operating range (?40 to +85 c) 11-pin quad flat no-lead (qfn) tiny 3 x 3 mm pcb footprint; pb-free, rohs-compliant ieee 802.3af endpoints and midspans environment a and b pses embedded pses set-top boxes ftth media converters cable modem and dsl gateways pin assignments 11-pin qfn (3x3 mm) top view?pads on bottom of package isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 ctrl1 gate ctrl2 vdd 250khz gnd SI3460 11 11 11 11
SI3460 2 preliminary rev. 0.4 1. block diagram figure 1. SI3460 block diagram deta rst status ctrl1 ctrl2 state machine control pwm dc/dc controller: uvlo, current limiting, short circuit protection otp memory pse controller: detection classification disconnect 250khz gate isense vsense config. & led i/f osc.
SI3460 preliminary rev. 0.4 3 t able of c ontents section page 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2. SI3460-evb applicat ion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1. SI3460-evb perform ance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. SI3460 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4. SI3460-evb performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1. pse timing charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2. dc-dc converter perfor mance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5. SI3460-evb functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1. reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2. operating mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3. operating mode sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1. isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2. external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3. input dc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6.4. status and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. SI3460 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. package outline: 11-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1. solder paste mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2. pcb landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.3. device marking of produc tion devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
SI3460 4 preliminary rev. 0.4 2. SI3460-evb application diagram figure 2. SI3460-evb application diagram 2.1. SI3460-evb perf ormance characteristics when implemented according to the recommended external components and layout guidelines for the SI3460- evb, the SI3460 enables the following performanc e specifications in single-port pse applications. please refer to the SI3460-evb user?s guide and schematics for details. table 1. selected electrical specifications (SI3460-evb) parameter symbol test condition min typ max unit power supplies v in input supply range v in ?40 to +85 c ambient range 11 12, 15 16 v v in input uvlo voltage uvlo uvlo turn-off voltage at v in 10 ? ? v vdd supply voltage range v dd SI3460 supply voltage range 2.7 3.3 3.6 v vdd uvlo voltage v ddmin SI3460 uvlo turn-off voltage 2.7 ? ? v output supply voltage v out pse output voltage at v in = 11 v (min) to 16 v (max) ?54 ?50 ?46 v supply current i in current into v dd (including gate drive and detect) ?5?ma detection specifications minimum signature resistance r detmin 15 17 19 k maximum signature resistance r detmax 26.5 29 33 k classification specifications classification voltage v class 0ma < i class < 45 ma ?20.5 ? ?15.5 v classification current limit i class measured with 200 across v out 55 ? 95 ma classification current region i class _ region class 0 0 ? 5 ma class 1 8 ? 13 ma class 2 16 ? 21 ma class 3 25 ? 31 ma class 4 35 ? 45 ma SI3460 gnd deta v in +11v to 16v v out -48 v pse output (to port magnetics) rst vdd pwm bom detect bom isense v ee status 250khz ctrl1 gate vsense detect fault pgood ctrl2 note: refer to the SI3460- evb user guide for complete schematic details
SI3460 preliminary rev. 0.4 5 protection and current control overload current threshold i cut all class levels 15,400/ v out 340 400 ma overload current limit i lim output = 100 across v out 400 425 450 ma overload time t lim output = 100 across v out 50 60 75 ms output power at overload p lim 15.4 17 ? w disconnect current i min disconnect current 5 7.5 10 ma efficiency system efficiency (p in @ v in ) to (p out @ v out )?75?% table 1. selected electrical specifications (SI3460-evb) parameter symbol test condition min typ max unit
SI3460 6 preliminary rev. 0.4 3. SI3460 electri cal specifications the following specifications apply to the SI3460 controller. refer to tables 1, 5, 6, and 7, the SI3460-evb user?s guide, and schematics for additional details about the electrical specificat ions of the SI3460- evb reference design. table 2. recommended operating conditions* description symbol test conditions min typ max unit operating temperature range t a ?40 25 +85 c thermal impedance ja no airflow 75 c/w vdd input supply voltage vdd during all operating modes (detect, classification, disconnect) 2.7 3.3 3.6 v *note: vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. table 3. absolute maximum ratings* parameter conditions max rating unit ambient temperature under bias ?55 to +125 c storage temperature ?65 to +150 c voltage on rst or any i/o pin with respect to gnd vdd > 2.2 v ?0.3 to 5.8 v voltage on vdd with respect to gnd ?0.3 to 4.2 v maximum total current through vdd and gnd 500 ma maximum output current into gate, ctrl1, ctrl2, 250khz, status, isense, rst , vsense, deta (any i/o pin) 100 ma esd tolerance human body model ?2 kv to +2 kv v lead temperature soldering, 10 seconds maximum 260 c *note: stresses above those listed in this table may cause permanent device damage. this is a stress rating only, and functional operation of the devices at thes e or any conditions above those indicat ed in the operational listings of this specification is not implied. exposure to maximum rating cond itions for extended periods may affect device reliability.
SI3460 preliminary rev. 0.4 7 table 4. electrical characteristics* description symbol test conditions min typ max unit digital pins: gate, ctrl1, ctrl2, 250khz, status (output mode), rst output high voltage v oh i oh =?3ma i oh =?10a i oh = ?10 ma 0.8 x vdd vdd ? 0.1 ? ? ? 0.7 x vdd ? ? ? v output low voltage v ol i ol =8.5ma i ol =10a i ol =25ma ? ? ? ? ? 0.4 x vdd 0.6 0.1 ? v input high voltage v ih any digital pin 0.7 x vdd v input low voltage v il any digital pin ? ? 0.3 x vdd v input leakage current i il v in =0v ? 1 ? a analog pins: isense, vsense, deta, status (input mode) input capacitance ?5?pf input leakage current i il ?1?a *note: vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified.
SI3460 8 preliminary rev. 0.4 4. SI3460-evb perfor mance characteristics when implemented in accordance with the recommended ex ternal components and layout guidelines, the SI3460 controller enables the followi ng typical performance characteristics in single-port pse applicat ions. refer to the SI3460-evb applications note, schematics, and user's guide for more details. table 5. pse performance characteristics 1 parameter symbol conditions min typ max unit protection and current control overload current threshold i cut all class levels 15,400/ v out 340 400 ma overload current limit i lim output = 100 across v out 400 425 450 ma overload time t lim output = 100 across v out 50 60 75 ms output power at overload p lim 15.4 17 ? w disconnect current i min disconnect current 5 7.5 10 ma detection specifications 2 detection voltage v det detection point 1 (w/ 10 k source) detection point 2 (w/ 10 k source) detection point 3 (w/ 10 k source) 4.5 7.5 4.5 v minimum signature resistance r detmin 15 17 19 k maximum signature resistance r detmax 26.5 29 33 k classification specifications 2 classification voltage v class 0 ma < iclass < 45 ma ?20.5 ?15.5 v classification current limit i class measured with 200 across v out 55 95 ma classification current region 3 i class_region class 0 class 1 class 2 class 3 class 4 0 8 16 25 35 5 13 21 31 45 ma ma ma ma ma notes: 1. typical specifications are based on an am bient operating temperature of 25 oc and v in = +12 v unless otherwise specified. 2. see ?4. SI3460-evb performance characteristics? for more details. 3. absolute classification curre nt limits are programmable.
SI3460 preliminary rev. 0.4 9 4.1. pse timing characteristics when implemented in accordance with the recommended ex ternal components and layout guidelines, the SI3460 controller enables the followi ng typical performance characteristics in single-port pse applicat ions. refer to the SI3460-evb applications note, schematics, and user's guide for more details. 4.1.1. pse timing diagrams the basic sequence of applying power is shown in figure 3. following is the description of the function that must be performed in each phase. figure 3. detection, classification, powerup, and disconnect sequence table 6. pse timing* description symbol test conditions min typ max unit endpoint detection delay cycle t det_cycle time from pd connection to port to completion of detection process. 70 400 ms detection time t detect time required to measure pd sig- nature resistance. 70 ms classification delay cycle t class_cycle time from successful detect mode to classification complete. 10 50 ms classification time t class 10 50 ms power-up turn-on delay t pwrup time from when a valid detection is completed until v out power is applied 30 ms midspan detect backoff time t bom 2s current limit time t lim 60 ms disconnect delay t dc_dis 350 ms *note: these typical specifications are based on an ambient operating temperature of 25 oc and v in =+12v. voltage t det_cycle time (msec) 2.8 v 10 v 15.5 v 44 v 57 v 20.5 v t class_cycle t pwrup
SI3460 10 preliminary rev. 0.4 4.2. dc-dc converter pe rformance characteristics the dc-dc converter utilizes a digital control loop architecture operating at 250 khz. th e complete converter is comprised of the SI3460 controller and the external co mponents in the SI3460-evb schematics. the performance specifications in table 7 are typical for the SI3460-evb reference design. table 7. dc-dc performance 1 parameter symbol conditions min typ max unit dc-dc controller perfo rmance characteristics 2 pwm operating frequency f pwm 250 khz efficiency v in to v out 75 % load regulation r load minimum to maximum load 1 % line regulation r line for v in ranging from 11 to 16 v 1 % output ripple r 250 khz pwm frequency < 500 hz 100 200 mv notes: 1. typical specifications are based on an am bient operating temperature of 25 oc and v in =+12v. 2. see ?4. SI3460-evb performance characteristics? for more details.
SI3460 preliminary rev. 0.4 11 5. SI3460-evb functional description in combination with low-cost exter nal components, the SI3460 controller provides a co mplete pse solution for embedded poe applications. in cluded in the SI3460-evb re ference design is a digital pwm controller-based dc-dc converter that simplifies overall system design by generat ing the ?48 v pse supply voltage. an isolated 11 to 16 v input dc supply is all that is needed to supply the SI3460-evb reference design. refer to the SI3460-evb user?s guide and schematics for descriptions in the following sections. 5.1. reset state at powerup or if reset is held low, the SI3460 is in an inactive state with the pwm turned off (the switcher fet, m1, is off) and the pass fet, m2, is off. 5.2. operating mode configuration at powerup, the SI3460 reads the voltage on the status pin, which is set by a resistor divider from v ee to chip ground. the status pin voltage level configures all of the SI3460's operating modes as summarized in table 8. table 8. operating modes status pin voltage operating mode power level supported (w) classes supported midspan/ endpoint restart action on fault or overload event condition pin voltage at v ee (no resistors populated) 15.4 all class levels endpoint auto restart after 2 s 3.0 v 7.0 class 1 or 2 endpoint auto restart after 2 s 2.75 v 4.0 class 1 endpoint auto restart after 2 s 2.5 v 15.4 all class levels endpoint restart on rst 2.25 v 7.0 class 1 or 2 endpoint restart on rst 2.0 v 4.0 class 1 endpoint restart on rst 1.75 v 4.0 class 1 midspan restart on rst 1.5 v 7.0 class 1 or 2 midspan restart on rst 1.25 v 15.4 all class levels midspan restart on rst 1.0 v 4.0 class 1 midspan auto restart after 2 s 0.5 v 7.0 class 1 or 2 midspan auto restart after 2 s < 0.25 v (pullup resistor only) 15.4 all class levels midspan auto restart after 2 s
SI3460 12 preliminary rev. 0.4 after powerup, the status pin drives the base of a pnp tr ansistor that controls an le d. to maintain an accurate voltage level at the transistor base, it is recommended that the parallel resistance setting the pin voltage be less than 1 k . 5.3. operating mode sequencing 5.3.1. detection after powerup and passing the uvlo threshold voltage of 10 v, the SI3460 enters into the detection state, with fet m2 off and the dc-dc conv erter disabled so as to g enerate no out put. prior to turnin g on the pse output fet m2 and enabling the 250 khz square wave for the dc-dc converter, a valid detection sequence must take place. according to the ieee specificat ions, the detection process consists of sensing a nominal 25 k signature resistance in parallel with up to 0.15 f of capacitance. to eliminate the possibility of false detection events, the SI3460-evb reference design pe rforms a robust 3-po int detection sequen ce by varying the voltage across the sense bridge r1, r2, and r3. the fourth leg of the sense bridge is the load that connects to the drain of m2 and returns to v ee via d8 and l1. at the beginning of the detection sequence, v out is at zero output voltage for 250 ms. with a 10 k source impedance, v out is then varied from 4.5 to 7.5 v and then back to 4.5 v for 20 ms at each level. if the pd's signature resistance is in the rgood range of 19 to 26.5 k , the SI3460 proceeds to classification and powerup. if the pd resistance is not in this range, the detection sequence repeats continuously. detection is sequenced approximately every 320 msec an d repeats until rgood is sensed, indicating a valid pd has been detected. the status led (d13) is flashed at the 320 ms rate in synchr onization with the detection process to indicate the pse is searching for a valid pd. 5.3.2. classification after a valid pd is detected, the pass transistor, m2, and the pwm controller are turned on and programmed for an output voltage of 18 v with a current limit of 75 ma. the current measured during the classification process determines the class level of the pd. if the class level of the pd is not within th e supported level as set by the initial voltage on the SI3460's status pin (refer to the op erating mode configuration section above), an error is declared and the led blinks rapidly. if the class level is in the supported range, the SI3460 proceeds to powerup. classification level is determin ed according to the current at isense as shown in table 9. if the classification level is at a greater power than c an be supported based on r28 and r30, an error condition is reported by flashing the led at a 10 hz rate for two se conds before the state machine goes back to the detection cycle. 5.3.3. dc-dc conv erter ramp-up after the optional classification seque nce, the dc-dc converter is powered up to ?50 v with a current limit corresponding to 430 ma. after powerup, power is applied to v out as long as there is not an overcurrent fault, disconnect, or input undervoltage (uvl o) condition. the status led is cont inuously lit when power is applied. if the output power exceed s the level determined by the in itial voltage of the status pin, the SI3460 will declare an error and shut down the port, flashing the led rapidly to indi cate the error (for either two seconds or until reset as determined by the initial vo ltage on the status pin). table 9. classification levels isense current (nominal) classification level minimum power level < 6.5 ma class 0 15.4 w 6.5ma to 14.5 ma class 1 4 w 14.5 ma to 23 ma class 2 7 w > 23 ma class 3 or 4 15.4 w
SI3460 preliminary rev. 0.4 13 5.3.4. dc-dc converter soft start the pwm control loop of the dc-dc converter is designed to produce a gradual rise in output voltage to eliminate any inrush current issues. the nominal set point of the dc-dc converter is ?50 v. v out at ?50 v results in 0.930 v at the vsense pin. it is possible for there to be almost no load on the dc-d c converter; so, the duty cycle is ramped slowly up to the dc set point. the duty cyc le is initially set to zero (dc-dc converter off). once the desired voltage set point is reached, the feedback path from vsense is enabled, and the converter is allo wed to regulate at the desired set point. 5.3.5. disconnect the SI3460 implements a robust disconnec t algorithm. if the output current level drops below 7.5 ma (nominal) for more than 350 msec, the SI3460 will declare a pd disc onnect, and the dc-dc converter clock (250 khz) and fet m1 will be turned off. as set by the initial voltage on the status pin, the SI3460 will t hen automatically resume the detection process after 250 ms for "endpoint mode" and two seconds for "midspan mode." the difference in these two backoff timings is specified by the iee 802.3af st andard for the midspan and endpoint operating modes. 5.3.6. current limit control the SI3460's overcurrent trip point is set to 340 ma (n ominal), corresponding to 17 w of output power for a nominal v out voltage of ?50 v. if the output current exceeds 340 ma, a timer counts up towards a time-out of 60 ms. if the current drops below 340 ma, the timer count s down towards zero at 1/16th the rate. if the timer reaches 60 msec, an overcurrent fault is declared, and the ch annel is shut down by turning off the dc-dc converter clock and then turning off fet m1. after an overcurrent fault event, the led is flashed rapidly. as set by the initial voltage on the status pin at power-up, the SI3460 will then either automatic ally resume the detection process (restart on fault or overload mode) or wait until rst is asserted (restart on reset) before the detect process resumes. 5.3.7. uvlo the SI3460-evb reference design is optimized for 12 to 15 v nominal in put voltages (11 v min to 16 v maximum). if the input voltage drops below 10 v in detection mode or if the output voltage drops below 10 v in classification or powerup mode, a uvlo condition is declared, which gene rates the error condition (led flashing rapidly). an undervoltage event is a fault condition reported throug h the status led as a rapid blinking of 10 flashes per second. the uvlo condition is continuously monitored in all operating states. 5.3.8. status led function during the normal detection sequence, the status led flashes approximately three times per second as the detection process continues. after succe ssful powerup, the led glows continuously. if there is an error condition (i.e. class level is beyond programmed value or a fault or overcurrent condition has been detected), the led flashes rapidly 10 times per second). this occurs for two seconds fo r normal error delay and will continue until reset if this operational mode is set. if the powered device (pd) is disconn ected so that a disconnect event occu rs, the led will start flashing three times per second once the detect process resumes.
SI3460 14 preliminary rev. 0.4 6. design considerations 6.1. isolation the SI3460-evb's pse ou tput power at v out is not isolated from the input power source (v in ). isolation of pse output power requires that the input be isolated from earth ground. typically, an ac to dc power supply or "wall wart" is used to provide the 12 v power so the output of this supply is isolated from earth ground. 6.2. external component selection detailed notes on extern al component selectio n are provided in t he SI3460-evb user's guide schematics and bom. in general, these reco mmendations must be followed closely to ensure output power stability and ripple (power stage components), surge protection (surge protection diode), and ov erall ieee 802. 3 compliance. 6.3. input dc supply the input power supply should be rated for at least 25% higher power level than the output power level chosen. this is primarily to account for the 75 to 80% nominal efficiency perf ormance of the SI3460 -evb reference design. for example, to support a class 0 pse, for example, the input supply shou ld be capable of supplying 19.25 w (15.4 w x 1.25 = 19.25 w). 6.4. status and reset interface to reference the reset and status pins to system grou nd, the level shifting method shown in figure 4 can be used. refer to the schemati c in the SI3460-evb document. figure 4. status and reset pin interfa ce when referenced to system ground vdd SI3460 status rst gnd +12v +8.7v status output shunt regulator r*3.3/2.7 rst control r8 (66.5 k ) r7 (40.2 k ) 806 system gnd 405 r40 (332 ) 1 uf/ 6.3 v r22 (1 k ) u1 tlv431
SI3460 preliminary rev. 0.4 15 7. SI3460 pin descriptions SI3460 pin functionality is described in table 10. note that the information applies to the SI3460 device pins, while the SI3460-evb user?s guide describes the inpu ts and outputs of th e evaluation system. the electrical characteri stics of the SI3460-evb are summariz ed in table 1, ?si3 460-evb performance characteristics summary,? on page 4. refer to the complete SI3460-evb schematics and bom listing for information abou t the external component s needed for the complete pse and dc-dc controlle r application circuit. table 10. SI3460 pin functionality pin # pin name pin type pin function 1 gate digital output a logic low on this pin turns on the output fet to enable the pse output voltage. refer to the si34 60-evb schematics for the circuit connections between the external fet and this pin. 2 ctrl1 digital output the output of this pin is averaged with ctrl2 to control pwm duty cycle for the dc-dc controller. this ou tput also controls the dc output for the detection circuitry. 3 vdd power 3.3 v power supply input. 4 ctrl2 digital output the output of this pin is averaged with ctrl1 to control pwm duty cycle for the dc-dc controller. this ou tput also controls the dc output for the detection circuitry. 5 250khz digital output this is a 250 khz square wave (50% duty cycle) that is filtered into a triangular wave signal for the dc-dc controller. the 250 khz out- put on this pin is gated off when it is desired to keep the switcher fet off. 6 deta analog input deta is an analog input pin. du ring the detection process, the ctrl1 and ctrl2 pin duty cycle is varied to generate filtered dc voltages across a resistive bridge. the null indicator for this bridge is connected to pin deta. 7 vsense analog input vsense is an analog input used fo r sensing the pse output volt- age. isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 ctrl1 gate ctrl2 vdd 250khz gnd 11 11 11 11
SI3460 16 preliminary rev. 0.4 8rst digital input active low reset inpu t. when low (to gnd), places the SI3460 device into an inactive state. the dc-dc converter is disabled. when pulled high, the device begins the detection process sequence. the dc-dc begins to function after a valid r good signa- ture is detected, indicating a valid pd has been detected. 9 isense analog input isense is an analog input connected to a current sense resistor for output current sensing. 10 status analog in/digital out at powerup, the voltage on this pin is sensed to configure the clas- sification level, mid span timi ng mode, and the device?s restart behavior when a fault condition is detected. refer to "5.2. operating mode configuration" on page 11 and "5.3.8. status led function" on page 13 for more information. after reading the voltage present at this pin at powerup, the status pin becomes a digital output used to control an external led, which indicates when a detect, power good, or output fault condition has occurred. a logic low turns the led on, and logic high turns the led off. 11 gnd gnd ground connection for the SI3460. this is not earth ground. refer to the si34 60-evb schematics for more info rmation. table 10. SI3460 pin functionality (continued) pin # pin name pin type pin function
SI3460 preliminary rev. 0.4 17 8. ordering guide ordering part number description package information temperature range (ambient) SI3460-xyy-gm single-port pse cont roller for embed- ded applications; extended tempera- ture range 11-pin qfn 3 x 3 mm rohs, pb-free ?40 to 85 c SI3460-evb single-port pse eval uation board and reference design evaluation board n/a notes: 1. ?x? denotes silicon revision. ? yy? denotes firmware revision. 2. add ?r? to part number for tape and reel option (e.g. SI3460-x-gmr). 3. the ordering part number above is not the same as the dev ice mark. the first line of the device mark is ?3460?. see "9.3. device marking of production de vices" on page 21 for more information.
SI3460 18 preliminary rev. 0.4 9. package outline: 11-pin qfn figure 5 illustrates the package details for the SI3460. table 11 lists the values for the dimensions shown in the illustration. the SI3460 is pa ckaged in an industry-sta ndard, 3x3 mm, rohs-compli ant, pb-free, 11-pin qfn package. figure 5. qfn-11 package drawing mm min typ max a 0.80 0.90 1.00 a1 00.020.05 a2 00.651.00 a3 ?0.25? b 0.18 0.23 0.30 d ?3.00? d2 ?2.202.25 d3 ?2.00? d4 ? 0.386 ? e ?3.00? e2 ?1.36? e3 ? 1.135 ? e ?0.5? k ?0.27? l 0.45 0.55 0.65 lb ?0.36? lt ?0.37? r 0.09 ? ? table 11. qfn-11 package dimensions a 1 e a3 a2 a side e view side d view e a1 a a3 a2 l b e e d e e2 d2 lt lb k b d4 bottom view r d2 e3
SI3460 preliminary rev. 0.4 19 9.1. solder paste mask figure 6. solder paste mask 0.50 mm lt e e d e lb k d2 b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm 0.30 mm 0.20 mm 0.60 mm 0.70 mm d4 b 0.30 mm 0.35 mm e2 0.20 mm
SI3460 20 preliminary rev. 0.4 9.2. pcb landing pattern figure 7. typical qfn-11 landing diagram lt e e d e lb k b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm d4 b 0.30 mm 0.20 mm e2 d2 0.10 mm
SI3460 preliminary rev. 0.4 21 9.3. device marking of production devices line 1 is the part number; line 2 is the lot code, and line 3 is the date code. the lot id c ode on the top side of the device package can be used for decoding device revision information. on SI3460 devices, the silicon revision letter is the first letter of the lot id code on the second line of the device mark . figure 8 shows how to find the lot id code on the top side of the device package for production devices. figure 8. qfn 11 device marking example 3460 dnzw 719+ first character identifies silicon revision
SI3460 22 preliminary rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: poeinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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